Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for forming an impurity region of a vertical transistor and a method for fabricating a vertical transistor using the same.
As mobile devices are widely spread and digital home appliances become smaller in size, the degree of integration of semiconductor memory devices constituting the mobile devices or the digital home appliances is increasing. Particularly, in the case of a DRAM device or a flash memory device, various attempts have been made to store a great quantity of information in a limited space. In general, a DRAM device is configured with a transistor and a capacitor, and has a stack structure in which the transistor is formed on a silicon semiconductor substrate and the capacitor is formed on the transistor.
For electrical connection between the transistor and the capacitor, a storage node contact is formed between a source region of the transistor and a lower electrode of the capacitor. In addition, a drain region of the transistor is electrically coupled to a bit line through a bit line contact. In the structure in which the capacitor is formed on the planar type transistor, layers for signal transmission (for example, a word line and a bit line) are formed between the transistor and the capacitor. However, there is a limitation in increasing the capacity of the capacitor due to the space occupied by the layers for signal transmission. Moreover, if a gate width of the planar type transistor is less than 40 nm, a larger amount of power may be consumed, and an amount of a body current, which is a leakage current between the source region and the drain region of the transistor, may increase. In this regard, researches related to a vertical transistor are being actively conducted.
FIG. 1 is a diagram explaining the basic concept of a vertical transistor. Referring to FIG. 1, the vertical transistor 100 has a structure in which a drain region 112 is formed at a lower portion of a silicon semiconductor substrate 110, and a source region 114 is formed at an upper portion of the silicon semiconductor substrate 110. A channel region 116 is formed between the drain region 112 and the source region 114, and a gate dielectric layer 118 and a gate electrode 120 are sequentially formed on the lateral side of the silicon semiconductor substrate 110 over the channel region 116. If the vertical transistor 100 is applied to a DRAM device, a bit line is coupled to the drain region 112 and a storage node is coupled to the source region 114. Since the bit line is formed to be buried in the side of the lower portion of the silicon semiconductor substrate 110, the space in which the storage node is to be formed may not decrease. Thus, data storage capacity may be improved in spite of high degree of integration. In addition, as the bit line is formed in a buried shape, bit line parasitic capacitance may decrease, and thus the height of the storage node may decrease by about ½ to ⅓.
However, in order to form the vertical transistor as described above, the drain region 112 may be formed at the lower portion of the silicon semiconductor substrate 110, but this process may be difficult to perform. An example of the process of forming the drain region 112 will be described below. Before forming the drain region 112, a side of the lower portion of the silicon semiconductor substrate 110 at which the drain region 112 is to be formed is opened. A metal layer into which impurities are doped with high concentration is formed to be in contact with the opened region. Then, the drain region 112 is formed by diffusing the impurities doped within the metal layer toward the silicon semiconductor substrate 110.
In this case, however, if the position opened for the formation of the drain region 112 is not exact, a cell threshold voltage may greatly change. As an example, if the position opened for the formation of the drain region 112 is too low, the drain region 112 is too far away from the gate electrode 120, causing a cell threshold voltage to increase. In addition, if the position opened for the formation of the drain region 112 is too high, an overlapping region between the drain region 112 and the gate electrode 120 increases. Thus, the length of the channel region decrease and the cell threshold voltage decreases, and thus a floating body structure in which holes are accumulated may be formed.
Furthermore, since the drain region 112 is formed by diffusing the impurities doped within the metal layer toward the silicon semiconductor substrate 110, it is difficult to adjust the concentration of the drain region 112. If the concentration of the drain region 112 is too low, an ohmic contact may not be formed in the region which is in contact with the metal layer constituting the bit line. Thus, a contact resistance may increase. On the other hand, if the concentration of the drain region 112 is too high, the impurities ions may be additionally diffused by a subsequent thermal treatment. Consequently, a floating body structure may be formed. That is, holes accumulated in the deep drain region 112 may not flow out.